Non-stick detection method and mechanism for array molded laminate packages

ABSTRACT

Embodiments of the present invention relate to a method and mechanism for testing wire bonds in an integrated circuit package. The method comprises bonding an integrated circuit silicon die to a package substrate. Next, wire connections are formed between pads in the integrated circuit silicon die and contact leads in the package substrate and testing each of the wire connections in order to detect non-stick failures using electrical continuity provided by the integrated circuit silicon die substrate. Electrical continuity is provided through dedicated pads in the package substrate that contact the underside of the silicon die substrate. The dedicated contact pads in each package substrate of the molded laminate array are connected to each other and to the mold gate. The continuity thus provided allows a non-stick-on-pad test by ensuring continuity between the wire spool through the die to the mold gate. Non-stick-on-lead check then looks for an open circuit between the wire spool and the mold gate which indicates a successful wire bond to the lead and associated separation from the wire feed capillary. The IC contact pads and leads in the package substrate are electrically isolated in order to allow functional testing and burn-in while the packaged integrated circuits are still in the laminate substrate array.

FIELD OF THE INVENTION

Embodiments of the present invention relate to the field of integratedcircuit packaging and testing.

BACKGROUND OF THE INVENTION

Manufacturing methods for integrated circuits have kept apace of, and inmany cases enable, developments in the integrated circuits themselves.The ever smaller feature architecture within IC's has been accompaniedby the technology that allows ever smaller packaging of the IC chips.Size, time and cost of IC production have all continued to shrink attremendous rates.

Testing techniques associated with the various stages of IC packaginghas been pressed to keep up with developments in the other areas ofproduction. As new methods of connecting IC's into the surroundingelectronic world have emerged, some older testing regimens have been arestriction on some developments.

Among the many packaging techniques that has emerged in recent years isthe ball grid array (BGA). An improvement on earlier surface mounttechnology, BGA has allowed orders of magnitude improvements in speed,miniaturization and reliability of packaged IC's.

In BGA packaging, the array of solder pads that lends the name to thetechnique are typically mounted on one surface of a tiny printed circuitboard (PCB), not much larger than the IC die itself, and made of a verythin substrate. The IC die is bonded and wired to connections on theopposite side of the small PCB using microscopic connections.

Typically, the small BGA PCB's are constructed in relatively large,array molded, laminate substrate sheets. By obviating the need for thelong lead fingers of the prior lead frame array associated with previoussurface mount technology, BGA packaging allows relatively dense arraysof units in process. The IC's are each bonded to the appropriatepositions on the laminate substrate while the small BGA PCB's are stillattached to each other. After bonding the dies to the substrate tracesand testing the connections, the sheets are generally separated intoindividual units for functional testing.

Commonly, in this process in which multiple BGA units occupy the samelaminate substrate strip, the individual traces on each of the units areconnected to a common bus line (109, FIG. 1A) in order to allow anelectrolytic plating process for Gold/Nickel plating, in anelectro-plated substrate. These bus lines are eventually connected tothe mold gate. This is called a “standard bus design” type packagingsubstrate.

During wire-bonding of such substrates, wire non-stick-on-pad (NSOP) andnon-stick-on-lead (NSOL) conditions can be detected to avoid wire bondfailures in assembly. This is done by using the electrical circuit asshown in conventional art FIG. 1A. The bus enabled circuit is formedafter bonding IC 102 to BGA substrate 101 and wire-bonding first wireconnection 106. The circuit closure is made through the gold wire in thespool, 105, the wire on the bond pad 106, to the lead finger 107 usingthe first wirebond 108, to bus-line 109 from lead fingers and finally tothe mold gate 110.

The mold gate is grounded to the wire bond clamp. Using this circuit, ifthere is a bad bond on either the bond pad or lead finger, the circuitis affected, and the bond's quality can be easily measured electrically.Similar technology is used in leadframe based assembly, where the dieattach pad is grounded to the wire bond clamp, through the leadframe,and is used for Non stick detection (NSD).

Since all the individual IC dies in a standard bus design substrate areconnected electrically to each other via the bus lines, they cannot betested, or burnt-in, in strip form and must be separated before beinghandled and tested as individual units. Also, since the first circuit isnot completed until the first bond is completed on both ball pad sideand lead finger side, the first ball bond NSOP detection has to beskipped in the wire-bond test step. For all successive bonds, this firstbond serves as the electrical connection between the silicon and thelead fingers for grounding to the mold gate. If a no-bus type substratedesign is used, in order to allow for in-strip testing, there is no NSOcapability since the electrical circuit is not completed back to themold gate in the absence of the bus-line connection. Conventional ArtFIG. 1B illustrates a no-bus design. Lead fingers 107 are isolated fromeach other and from mold gate grounding 110. The result is an opencircuit 105 and an inability to check for proper sticking in connectionwire 106.

The current art, then, is disadvantageous because the prevalent andmethod of NSD requires that lead fingers be grounded which prohibitsin-strip functional testing and burn-in of the packaged ICs.

SUMMARY OF THE INVENTION

Presented herein is a method for performing non-stick detection in a BGApackaging substrate array strip that does not require a bus connectingall leads and pads together. Furthermore, the testing method allows theassembled BGA packages to be functionally tested while still in thearray strip.

More specifically, embodiments of the present invention relate to amethod and mechanism for testing wire bonds in an integrated circuitpackage. The method comprises bonding an integrated circuit silicon dieto a package substrate. Next, wire connections are formed between padsin the integrated circuit silicon die and contact leads in the packagesubstrate and testing each of the wire connections in order to detectnon-stick failures using electrical continuity provided by theintegrated circuit silicon die substrate. Electrical continuity isprovided through dedicated pads in the package substrate that contactthe underside of the silicon die substrate. The dedicated contact padsin each package substrate of the molded laminate array are connected toeach other and to the mold gate. The continuity thus provided allows anon-stick-on-pad test by ensuring continuity between the wire spoolthrough the die to the mold gate. Non-stick-on-lead check then looks foran open circuit between the wire spool and the mold gate which indicatesa successful wire bond to the lead and associated separation from thewire feed capillary. The IC contact pads and leads in the packagesubstrate are electrically isolated in order to allow functional testingand burn-in while the packaged integrated circuits are still in thelaminate substrate array.

These and other objects and advantages of the present invention willbecome obvious to those of ordinary skill in the art after having readthe following detailed description of the preferred embodiments whichare illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The operation and components of this invention can be best visualized byreference to the drawings.

Conventional Art FIG. 1A illustrates conventional NSD testing in abus-connected array.

Conventional Art FIG. 1B illustrates a failure of conventional NSDtesting in a non-bus-connected array.

FIG. 2 illustrates array molded laminate substrates with NSD pad and busin accordance with one embodiment of the present invention.

FIG. 3 illustrates non-stick on pad (NSOP) detection in accordance withone embodiment of the present invention.

FIG. 4 illustrates non-stick on lead (NSOL) detection in accordance withone embodiment of the present invention.

FIG. 5 illustrates a non-stick detection method in flowchart form.

DETAILED DESCRIPTION

Reference will now be made in detail to the preferred embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. While the invention will be described in conjunction with thepreferred embodiments, it will be understood that they are not intendedto limit the invention to these embodiments. On the contrary, theinvention is intended to cover alternatives, modifications andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims. Furthermore, in thefollowing detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be obvious toone of ordinary skill in the art that the present invention may bepracticed without these specific details. In other instances, well-knownmethods, procedures, components, and circuits have not been described indetail so as not to unnecessarily obscure aspects of the presentinvention. At times, concepts disclosed in this embodiment of thepresent invention will be made more readily apparent be reference to theFigures.

Embodiments of the present invention discussed herein relate to testingmethods in the packaging process of integrated circuit production. Inthis embodiment, the electrical path for testing the wire bonding ofeach unit is completed through the die backside, connecting to a specialmetal pad under the die, to be used only for NSD. In thisimplementation, the die backside is grounded to a special NSD trace onthe substrate die paddle area. This trace metal land is not covered bythe solder mask coating, so that there is electrical contact between thedie backside and this trace land via the conductive die attach material.Note that, being uncoated, the metal land is easily etched backsubsequent to NSD.

These special NSD traces are connected to a bus line and shorted back tothe mold gate. The traces can be connected to the bus line used forplating the lead fingers or an additional bus line. These bus lines canbe on either the top or bottom metal layer of the substrate. In case ofconnection using the bottom metal layer, the traces are connected totraces on the bottom of the substrate using drilled and plated vias. Thebus-lines on the bottom layer are then connected back to the mold gateon the top layer using another plated through hole via under the moldgate.

FIG. 2 illustrates a possible location for the dedicated NSD contactpads 220 in packaging substrates in a molded laminate array. Dedicatedpads 220 are shown connected by traces 215 to NSD bus 210. Bus 210connects NSD pads in other substrates in the substrate array as well.Note specifically that lead fingers 107 are not connected to each othernor to mold gate bus 110, making FIG. 2 an illustration of a no-busdesign array.

In the case of a “bus design,” there can be two sets of bus lines, oneused in the electrolytic plating of traces connected to the leadfingers, and another for bus-connecting the special NSD traces under thedie. This allows selectively etching back the lead finger plating buslines, without etching back the NSD trace bus line, to subsequentlyachieve a “no-bus” design.

In both bus and no-bus cases, this embodiment of the present inventionallows a first ball bond NSD since the electrical circuit is completethrough the gold wire in spool, the wire in the capillary, the diesilicon, the electrically conductive die attach material, the non-stickdetection trace under die, the bus line and, finally, the mold gate,which is grounded.

The circuit connection for NSD is illustrated in FIG. 3. Here, testcircuit 105 is shown completed during NSOP testing. Wire bond 106 hasbeen attached to a pad on IC die 102 which is bonded using bonding epoxy212 to packaging substrate 101. Continuity to dedicated NSD pad 220through the substrate silicon of die 102 is shown at 221. NSD pad 220 isconnected via a trace 215 in a routing layer in substrate 101 to NSD busline 210 and then to ground. Non-stick would be indicated by an opencircuit 105.

Similarly, FIG. 4 illustrates NSOL testing. Here testing indicates astick failure when circuit 105 is completed through the bonding wire.Wire bonds are made, in this embodiment, by attaching the die pad endfirst, checking NSOP, then bonding the lead end. A successful bondingresults in separation of the wire from the wire feed capillary 104. Ifthe wire bonding fails to stick to the lead contact pad, then thatfailure is indicated by circuit 105 remaining closed. A successful stickwould be indicated by an open circuit.

In this implementation of this embodiment of the present invention thereare two of the dedicated NSD traces on each die attach area, bothconnected to the bus lines and to each other. This could allow anelectrical path between bus lines of adjacent die paddle units; evenwhen the die is absent. Since substrate production typically producesless than 100% yields, it is common to get some reject spots on thesubstrate where a die attachment is skipped. If the two traces are notconnected to each other, then a conductive path through the die attachmaterial between them would be necessary.

Implementations of this embodiment of the present invention can alsosupport NSD in processes using non-conductive die attach paste. In sucha case, an implementation could be modified in the following manner. Anyone of the lead fingers of each die paddle unit can be shorted andgrounded to the mold gate, the lead finger to be used being selectedbased on the functionality of that lead finger. A common choice would bea ground pin finger.

During wire bonding, the first ball bond NSOP test would initially beskipped and the first wire bond to the grounded lead finger would beused as the electrical circuit completion for NSD of all the otherwires, the continuity for which would an ohmic connection through thedie material. This implementation would allow for etch-back ofsubstrates in applications that use non-conductive die attach materialas well. A wire bonder could be programmed to return to and check thefirst ball-bond NSOP at a later stage in the process. In most cases theground pin lead finger can be used as the pin shorted to the mold gatefor NSD.

This embodiment of the present invention allows true NSD for both NSOPand NSOL on all BGA packages, irrespective of the plating bus bardesign, or fabrication methods, for every wire bond. This embodimentenables the capability of testing BGA units in strip form, as well asburn-in of the units in strip form. The cost and time savings ofenabling bulk handling in these processes while still attached in stripform should be readily apparent. The savings would include reducing thetest and burn-in costs by eliminating package-dimension-specific testsockets, burn-in sockets and boards. Process cycle time as well as costsrelated to package changeover can be eliminated using this embodiment.

Plastic BGA packages, in larger package sizes, can use a gold plated dieattach paddle under the die as a grounding for NSD in this embodiment.However this is possible only if routing for the BGA contact pads doesnot use this space. Smaller BGA's, often referred to as Fine pitch BGA(FBGA) use the area under the die for trace routing and a die attachpaddle implementation must take routing into account.

FIG. 5 illustrates the NSD method described herein in flowchart form.Method 500 starts by bonding the IC die to the packaging substrate, 510,then commencing the formation of wire bonding, 520. After bonding theconnection wire to the IC's circuit contact pad, electrical continuityis checked, 530, from the wire spool through the wire feed capillary,the circuit contact pad, the IC die's silicon substrate, the dedicatedNSD contact pads on the packaging substrate, the grounding line tracesto the mold gate. If continuity does not exist 540 then a non-stickfailure is assumed and the bond is redone, 550. If continuity doesexist, there is no non-stick failure. The wire is then bonded at thelead contact pad on the packaging substrate, 560, and, if properlybonded, separates from the wire feed capillary. Then another continuitycheck is made, 570. If there is continuity at this point, 580, then thewire has failed to stick and a non-stick-on-lead failure is detected.The bond is reattempted, 590. If there is no continuity, then anon-stick is not detected and the process moves on, 599.

A new method for implementing non-stick detection for array-moldedlaminate packages without a plating bus has been described. Theforegoing descriptions of specific embodiments of the present inventionhave been presented for purposes of illustration and description. Theyare not intended to be exhaustive or to limit the invention to theprecise forms disclosed, and obviously many modifications and variationsare possible in light of the above teaching. The embodiments were chosenand described in order to best explain the principles of the inventionand its practical application, to thereby enable others skilled in theart to best utilize the invention and various embodiments with variousmodifications as are suited to the particular use contemplated. It isintended that the scope of the invention be defined by the claimsappended hereto and their equivalents.

1. A method for testing wire bonds in an integrated circuit package,comprising: receiving a die comprising an integrated circuit formed on asemiconductor substrate that is bonded to a packaging substrate, saidintegrated circuit comprising a circuit contact pad and said packagingsubstrate comprising a lead contact pad, wherein a non-stick detection(NSD) contact pad contacts said semiconductor substrate and extendsthrough said packaging substrate, said NSD contact pad coupled via atrace line to a bus line that is coupled to ground; forming a wireconnection between said circuit contact pad and said lead contact pad;and testing said wire connection for failure to stick at said circuitcontact pad and at said lead contact pad by checking for electricalcontinuity along a path comprising said circuit contact pad and said NSDcontact pad, wherein said semiconductor substrate itself provideselectrical continuity between said circuit contact pad and said NSDcontact pad for said testing.
 2. A method as described in claim 1,wherein said integrated circuit die is bonded to said packagingsubstrate using electrically conductive epoxy.
 3. A method as describedin claim 1, wherein said integrated circuit die is bonded to saidpackaging substrate using non-electrically conductive epoxy.
 4. A methodas described in claim 1, wherein said lead contact pad is electricallyisolated from other lead contact pads in said packaging substrate.
 5. Amethod as described in claim 1, wherein said method is performed for aplurality of wire connections.
 6. A method for testing wire bonds in anintegrated circuit package, comprising: receiving a die comprising anintegrated circuit formed on a semiconductor substrate, wherein saidintegrated circuit die is bonded to a packaging substrate; connectingone end of a wire to a circuit contact pad of said integrated circuit;and testing for failure of said wire to stick to said circuit contactpad by checking for electrical continuity along a path comprising saidcircuit contact pad and a non-stick detection (NSD) contact pad coupledto said semiconductor substrate, wherein said NSD contact pad extendsthrough said packaging substrate and wherein said semiconductorsubstrate provides electrical continuity between said circuit contactpad and said NSD contact pad for said testing.
 7. A method as describedin claim 6, wherein said NSD contact pad is coupled via a trace line toa bus line that is coupled to a grounded mold gate, wherein said pathfor checking electrical continuity further comprises said trace line,said bus line and said mold gate.
 8. The method of claim 7, wherein saidwire is fed from a wire spool and wherein said path for checkingelectrical continuity further comprises said wire and said wire spool.9. A method for testing wire bonds in an integrated circuit package,comprising: connecting the first end of a length of a wire fed from awire spool to a circuit contact pad in an integrated circuit formed on asemiconductor substrate that is bonded to a packaging substrate; andtesting said connecting of said first end of said wire to said circuitcontact pad for failure to stick by checking for electrical continuityon a path comprising, in order, said wire spool, said length of wire,said circuit contact pad, said semiconductor substrate, and a non-stickdetection (NSD) contact pad coupled to said semiconductor substrate,wherein said NSD contact pad extends through said packaging substrate,wherein said semiconductor substrate provides electrical continuitybetween said circuit contact pad and said NSD contact pad for saidtesting, wherein failure to stick at said first end is indicated if saidelectrical continuity does not exist.
 10. A method as described in claim9 wherein said NSD contact pad is coupled via a trace line to a bus linethat is coupled to a grounded mold gate, wherein said path for checkingelectrical continuity further comprises said trace line, said bus lineand said mold gate.
 11. A method as described in claim 9, furthercomprising: connecting the second end of said length of wire to a leadcontact pad in said packaging substrate, wherein successful connectionof said second end to said lead contact pad causes said length of wireto separate from said wire spool; and testing connection of said secondend to said lead contact pad for failure to stick by checking forelectrical continuity along said path, wherein failure to stick at saidsecond end is indicated if electrical continuity exists.